Usually ,in MSDOS ,the primary hard disk drives has the drive letter_______ A B C D ____________________________________...
Usually ,in MSDOS ,the primary hard disk drives has the drive letter_______
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P : “Program is a step by step execution of the instructions”. Given P, which of the following is true ?
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The most relevant addressing mode to write position independent code
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An interface that provides a method for transferring binary information between internal storage and external devices is called
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An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as
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In magnetic disk data organized on the plotter in a concentric sets or rings called
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In which addressing mode the operand is given explicitly in the instruction
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The instruction: MOV CL, [BX] [DI] + 8 represents the _____ addressing mode.
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A basic instruction that can be interpreted by computer generally has
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The two types of main memory are
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A hardware unit which is used to monitor computer processing is
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On receiving an interrupt from an I/O device, the CPU
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ADC
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The concept of pipelining is most effective in improving performance if the tasks being performed in different stages
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Performance of a pipelined processor suffers if
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In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onward. The main memory block numbered j must be mapped to any one of the cache lines from
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For a memory system ,the cycle time is
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Secondary storage device which uses a delivery grooveless surface and is encoded by the laser beam in the form of microscopic pits is called
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The addressing mode used in the instruction PUSH B is
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The idea of cache memory is based on
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Where does a computer add and compare data ?
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The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio :
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The register used as a working area in CPU is
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The ALU of a microprocessor performs operations on 8 bit two complement operands. What happens when the operation 7A16-A216 is performed?
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An interrupt can be temporarily ignored by the counter is called
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A CPU generally handles an interrupt by executing an interrupt service routine
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A single instruction to clear lower 4 bits of the accumulator in 8085 assembly language is
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Which out of the following is not an alternative name for primary memory?
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Which of the following is a sequential access device
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The ALU of a computer normally contains a number of high speed storage elements called
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The control unit of computer
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WORM stands for
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The hardware in which data may be stored for a computer system is called
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The Pentium processor was introduced
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The circumferences of the two concentric disks are divided into 100 sections each. For the outer disk, 100 of the sections are painted red and 100 of the sections are painted blue. For the inner disk, the sections are painted red and blue in an arbitrary manner. It is possible to align the two disks so that of the sections on the inner disks have their colours matched with the corresponding section on outer disk.
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Interrupts which are initiated by an I/O drive are
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Arithmetic shift left operation
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Fetch_And_Add(X,i) is an atomic Read-Modify-Write instruction that reads the value of memory location X, increments it by the value i, and returns the old value of X. It is used in the pseudocode shown below to implement a busy-wait lock. L is an unsigned integer shared variable initialized to 0. The value of 0 corresponds to lock being available, while any non-zero value corresponds to the lock being not available. AcquireLock(L){ while (Fetch_And_Add(L,1)) L = 1; } ReleaseLock(L){ L = 0; } This implementation
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A control character is sent at the beginning as well as at the end of each block in the synchronous-transmission in order to
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The process of entering data into a storage location
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Of the following, which best characterizes computers that use memory-mapped I/O?
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The desirable characteristic of a memory system is
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In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from
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Intel 80486 was introduced in
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Which of the following are typical characteristics of a RISC machine?
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The amount of ROM needed to implement a 4 bit multiplier is
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On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock
cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
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A charge coupled device has
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WHAT IS A REGISTER?
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The bus which is used to transfer data from main memory to peripheral device is
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