Microprocessors 8086 Solved MCQs

This section contains more frequently asked Microprocessor-8086 MCQs Multiple Choice Questions Answers which are randomly compiled from various reference books and Questions papers for those who are preparing for the various University Level and Competitive Examinations.

1. A microprocessor is a _______ chip integrating all the functions of a CPU of a computer.

multiple
single
double
triple

B. single

2. Microprocessor is a/an _______ circuit that functions as the CPU of the compute

electronic
mechanic
integrating
processing

A. electronic

3. Microprocessor is the ______ of the computer and it perform all the computational tasks

main
heart
important
simple

B. heart

4. The purpose of the microprocessor is to control ______

memory
switches
processing
tasks

A. memory

5. The first digital electronic computer was built in the year________

1950
1960
1940
1930

C. 1940

6. In 1960’s texas institute invented ______

integrated circuits
microprocessor
vacuum tubes
transistors

A. integrated circuits

7. The intel 8086 microprocessor is a _______ processor

8 bit
16 bit
32 bit
4 bit

B. 16 bit

8. The microprocessor can read/write 16 bit data from or to ________

memory
I /O device
processor
register

A. memory

9. In 8086 microprocessor , the address bus is ________ bit wide

12 bit
10 bit
16 bit
20 bit

D. 20 bit

10. The work of EU is ________

encoding
decoding
processing
calculations

B. decoding

Set 2

1. The 16 bit flag of 8086 microprocessor is responsible to indicate ___________

the condition of result of ALU operation
the condition of memory
the result of addition
the result of subtraction

A. the condition of result of ALU operation

2. The CF is known as ________

carry flag
condition flag
common flag
single flag

A. carry flag

3. The SF is called as ________

service flag
sign flag
single flag
condition flag

B. sign flag

4. The OF is called as _______

overflow flag
overdue flag
one flag
over flag

A. overflow flag

5. The IF is called as _________

initial flag
indicate flag
interrupt flag
inter flag

C. interrupt flag

6. The register AX is formed by grouping ________

AH & AL
BH & BL
CH & CL
DH & DL

A. AH & AL

7. The SP is indicated by ________

single pointer
stack pointer
source pointer
destination pointer

B. stack pointer

8. The BP is indicated by _______

base pointer
binary pointer
bit pointer
digital pointer

A. base pointer

9. The SS is called as ________

single stack
stack segment
sequence stack
random stack

B. stack segment

10. The index register are used to hold _______

memory register
offset address
segment memory
offset memory

A. memory register

SET 3

1. The BIU contains FIFO register of size __________ bytes

B. 6

2. The BIU prefetches the instruction from memory and store them in ________

queue
register
memory
stack

A. queue

3. The 1 MB byte of memory can be divided into ______ segment

1 Kbyte
64 Kbyte
33 Kbyte
34 Kbyte

B. 64 Kbyte

4. The DS is called as _______

data segment
digital segment
divide segment
decode segment

A. data segment

5. The CS register stores instruction _____________ in code segment

stream
path
codes
stream line

C. codes

6. The IP is ________ bits in length

8 bits
4 bits
16 bits
32 bits

C. 16 bits

7. The push source copies a word from source to ______

stack
memory
register
destination

A. stack

8. LDs copies to consecutive words from memory to register and ___________

B. DS

9. INC destination increments the content of destination by _______

A. 1

10. IMUL source is a signed _________

multiplication
addition
subtraction
division

A. multiplication

SET 4

1. _________destination inverts each bit of destination

A. NOT

2. The JS is called as ______

jump the signed bit
jump single bit
jump simple bit
jump signal it

A. jump the signed bit

3. Instruction providing both segment base and offset address are called _____

below type
far type
low type
high type

B. far type

4. The conditional branch instruction specify ___________ for branching

conditions
instruction
address
memory

A. conditions

5. The microprocessor determines whether the specified condition exists or not by testing the ______

carry flag
conditional flag
common flag
sign flag

B. conditional flag

6. The LES copies to words from memory to register and __________

C. ES

7. The _________ translates a byte from one code to another code

XLAT
XCHNG
POP
PUSH

A. XLAT

8. The _______ contains an offset instead of actual address

B. IP

9. The 8086 fetches instruction one after another from __________ of memory

code segment
IP
ES
SS

A. code segment

10. The BIU contains FIFO register of size 6 bytes called _____.

queue
stack
segment
register

A. queue

SET 5

1. The ___________ is required to synchronize the internal operands in the processor CLK Signal

UR Signal
Vcc
AIE
Ground

A. UR Signal

2. The pin of minimum mode AD0-AD15 has ____________ address

16 bit
20 bit
32 bit
4 bit

B. 20 bit

3. The pin of minimum mode AD0- AD15 has _________ data bus

4 bit
20 bit
16 bit
32 bit

C. 16 bit

4. The address bits are sent out on lines through __________

A16-19
A0-17
D0-D17
C0-C17

A. A16-19

5. ________ is used to write into memory

RD
WR
RD / WR
CLK

B. WR

6. The functions of Pins from 24 to 31 depend on the mode in which _______ is operating

8085
8086
80835
80845

B. 8086

7. The RD, WR, M/IO is the heart of control for a __________ mode

minimum
maximum
compatibility mode
control mode

A. minimum

8. In a minimum mode there is a ___________ on the system bus

single
double
multiple
triple

A. single

9. If MN/MX is low the 8086 operates in __________ mode

Minimum
Maximum
both (A) and (B)
medium

B. Maximum

10. In max mode, control bus signal So,S1 and S2 are sent out in ____________ form

decoded
encoded
shared
unshared

B. encoded

SET 6

1. The ___ bus controller device decodes the signals to produce the control bus signal

internal
data
external
address

C. external

2. A _____ Instruction at the end of interrupt service program takes the execution back to the interrupted program

forward
return
data
line

B. return

3. The main concerns of the ___________ are to define a flexible set of commands

memory interface
peripheral interface
both (A) and (B)
control interface

A. memory interface

4. Primary function of memory interfacing is that the _________ should be able to read from and write into register

multiprocessor
microprocessor
dual Processor
coprocessor

B. microprocessor

5. To perform any operations, the Mp should identify the __________

register
memory
interface
system

A. register

6. The Microprocessor places __________ address on the address bus

4 bit
8 bit
16 bit
32 bit

C. 16 bit

7. The Microprocessor places 16 bit address on the add lines from that address by _____ register should be selected

address
one
two
three

B. one

8. The ________of the memory chip will identify and select the register for the EPROM

internal decoder
external decoder
address decoder
data decoder

A. internal decoder

9. Microprocessor provides signal like ____ to indicate the read operatio

LOW
MCMW
MCMR
MCMWR

C. MCMR

10. To interface memory with the microprocessor, connect register the lines of the address bus must be added to address lines of the _______ chip.

single
memory
multiple
triple

B. memory on

SET 7.

look

1. The remaining address line of ______ bus is decoded to generate chip select signal

data
address
control bus
both (a) and (b)

B. address

2. _______ signal is generated by combining RD and WR signals with IO/M

control
memory
register
system

A. control

3. Memory is an integral part of a _______ system

supercomputer
microcomputer
mini computer
mainframe computer

B. microcomputer

4. _____ has certain signal requirements write into and read from its registers

memory
register
both (a) and (b)
control

A. memory

5. An _________ is used to fetch one address

internal decoder
external decoder
encoder
register

A. internal decoder

6. The primary function of the _____________ is to accept data from I/P devices

multiprocessor
microprocessor
peripherals
interfaces

B. microprocessor

7. ___________ signal prevent the microprocessor from reading the same data more than one

pipelining
handshaking
controlling
signaling

B. handshaking

8. Bits in IRR interrupt are ______

reset
set
stop
start

B. set

9. __________ generate interrupt signal to microprocessor and receive acknowledge

priority resolver
control logic
interrupt request register
interrupt register

B. control logic

10. The _______ pin is used to select direct command word

A0
D7-D6
A12
AD7-AD6

A. A0

SET 8

1. The _______ is used to connect more microprocessor

peripheral device
cascade
I/O devices
control unit

B. cascade

2. CS connect the output of ______

encoder
decoder
slave program
buffer

B. decoder

3. In which year, 8086 was introduced?

1978
1979
1977
1981

A. 1978

4. Expansion for HMOS technology_______

high level mode oxygen semiconductor
high level metal oxygen semiconductor
high performance medium oxide semiconductor
high performance metal oxide semiconductor

D. high performance metal oxide semiconductor

5. 8086 and 8088 contains _______ transistors

29000
24000
34000
54000

A. 29000

6. ALE stands for ___________

address latch enable
address level enable
address leak enable
address leak extension

A. address latch enable

7. What is DEN?

direct enable
data entered
data enable
data encoding

C. data enable

8. In 8086, Example for Non maskable interrupts are ________.

TRAP
RST6.5
INTR
RST6.6

A. TRAP

9. In 8086 the overflow flag is set when _____________

the sum is more than 16 bits.
signed numbers go out of their range after an arithmetic operation.
carry and sign flags are set.
subtraction

B. signed numbers go out of their range after an arithmetic operation.

10. In 8086 microprocessor the following has the highest priority among all type interrupts?

NMI
DIV 0
TYPE 255
OVER FLOW

A. NMI

SET 9

1. In 8086 microprocessor one of the following statements is not true?

coprocessor is interfaced in max mode.
coprocessor is interfaced in min mode.
I /O can be interfaced in max / min mode.
supports pipelining

B. coprocessor is interfaced in min mode.

2. Address line for TRAP is?

0023H
0024H
0033H
0099H

B. 0024H

3. Access time is faster for _________

ROM
SRAM
DRAM
ERAM

B. SRAM

4. The First Microprocessor was__________

8080
8085
4008
Intel 4004

D. Intel 4004

5. Status register is also called as ___________

accumulator
stack
counter
flags

D. flags

6. Which of the following is not a basic element within the microprocessor?

Microcontroller
Arithmetic logic unit (ALU)
Register array
Control unit

A. Microcontroller

7. Which method bypasses the CPU for certain types of data transfer?

Software interrupts
Interrupt-driven I/O
Polled I/O
Direct memory access (DMA)

D. Direct memory access (DMA)

8. Which bus is bidirectional?

Address bus
Control bus
Data bus
None of the above

C. Data bus

9. The first microprocessor had a(n)________

1 – bit data bus
2 – bit data bus
4 – bit data bus
8 – bit data bus

C. 4 – bit data bus

10. Which microprocessor has multiplexed data and address lines?

8086
80286
80386
Pentium

A. 8086

SET 10

1. Which is not an operand?

Variable
Register
Memory location
Assembler

D. Assembler

2. Which is not part of the execution unit (EU)?

Arithmetic logic unit (ALU)
Clock
General registers
Flags

B. Clock

3. A 20-bit address bus can locate ________

1,048,576 locations
2,097,152 locations
4,194,304 locations
8,388,608 locations

A. 1,048,576 locations

4. Which of the following is not an arithmetic instruction?

INC (increment)
CMP (compare)
DEC (decrement)
ROL (rotate left)

D. ROL (rotate left)

5. During a read operation the CPU fetches ________

a program instruction
another address
data itself
all of the above

D. all of the above

6. Which of the following is not an 8086/8088 general-purpose register?

Code segment (CS)
Data segment (DS)
Stack segment (SS)
Address segment (AS)

D. Address segment (AS)

7. A 20-bit address bus allows access to a memory of capacity

1 MB
2 MB
4 MB
8 MB

A. 1 MB

8. Which microprocessor accepts the program written for 8086 without any changes?

8085
8086
8087
8088

D. 8088

9. Which group of instructions do not affect the flags?

Arithmetic operations
Logic operations
Data transfer operations
Branch operations

C. Data transfer operations

10. The result of MOV AL, 65 is to store

store 0100 0010 in AL
store 42H in AL
store 40H in AL
store 0100 0001 in AL

D. store 0100 0001 in AL

X8086 Microprocessor Solved MCQs

Microprocessors 8086 Solved MCQs

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