Usually ,in MSDOS ,the primary hard disk drives has the drive letter_______

A
B
C
D
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P : “Program is a step by step execution of the instructions”. Given P, which of the following is true ?

Program is a subset of an instruction set.
Program is a sequence of a subset of an instruction set.
Program is a partially ordered set of an instruction set.
All of the above
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The most relevant addressing mode to write position independent code 

Direct mode
Indirect mode
Relative mode
Indexed mode
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An interface that provides a method for transferring binary information between internal storage and external devices is called 

I/O interface
Input interface
Output interface
I/O bus
      _____________________________________________________________________________________
An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as 

DDA
Serial interface
BR
DMA
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In magnetic disk data organized on the plotter in a concentric sets or rings called

Sector
Track
Head
Block
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In which addressing mode the operand is given explicitly in the instruction

Absolute
Immediate
Indirect
Direct
      _____________________________________________________________________________________
The instruction: MOV CL, [BX] [DI] + 8 represents the _____ addressing mode.

Based Relative
Based Indexed
Indexed Relative
Register Indexed
      _____________________________________________________________________________________
A basic instruction that can be interpreted by computer generally has 

An operand and an address
A decoder and an accumulator
Sequence register and decoder
An address and decoder
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The two types of main memory are 

Primary and secondary
Random and sequential
ROM and RAM
Central and peripheral
      _____________________________________________________________________________________
A hardware unit which is used to monitor computer processing is

Console
Dot matrix printer
Mouse
ROM
      _____________________________________________________________________________________
On receiving an interrupt from an I/O device, the CPU

halts for predetermined time
branches off to the interrupt service routine after completion of the current instruction
branches off to the interrupt service routine immediately
hands over control of address bus and data bus to the interrupting device
      _____________________________________________________________________________________
ADC

Add to Accumulator using carry Flag
Add to Accumulator
Add Immediate data to Accumulator
Add Immediate data to Accumulator Using carry
      _____________________________________________________________________________________
The concept of pipelining is most effective in improving performance if the tasks being performed in different stages

Require different amount of time
Require about the same amount of time
Require different amount of time with time difference between any two tasks being same
Require different amount with time difference between any two tasks being different
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Performance of a pipelined processor suffers if 

The pipeline stages have different delays
Consecutive instructions are dependent on each other
The pipeline stages share hardware resources
All of these
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In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onward. The main memory block numbered j must be mapped to any one of the cache lines from

( j mod v)*k to ( j mod v)*k + (k -1)
( j mod v) to ( j mod v) + (k -1)
( j mod k) to ( j mod k) + (v -1)
( j mod k)* v to ( j mod k)* v + (v -1)
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For a memory system ,the cycle time is 

Same as the access time
Longer than the access time
Shorter than the access time
Submultiple of the access time
      _____________________________________________________________________________________
Secondary storage device which uses a delivery grooveless surface and is encoded by the laser beam in the form of microscopic pits is called

Laser disk
Compact disk
Photo disk
Video disk
      _____________________________________________________________________________________
The addressing mode used in the instruction PUSH B is

Direct
Register
Register indirect
Immediate
      _____________________________________________________________________________________
The idea of cache memory is based on

The property of locality of reference
The heuristic 90-10 rule
The fact that only a small portion of a program is referenced relatively frequently
All of these
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Where does a computer add and compare data ?

Hard disk
Floppy disk
CPU chip
Memory chip
      _____________________________________________________________________________________

The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio :


A
B
C
D
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The register used as a working area in CPU is 

Program counter
Instruction register
Instruction decoder
Accumulator
      _____________________________________________________________________________________
The ALU of a microprocessor performs operations on 8 bit two complement operands. What happens when the operation 7A16-A216 is performed?

Result = D816 , overflow and negative flags set
Result = D816 , negative flags set
Result = D816 ,no flags set
Result = D816 , overflow flags set
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An interrupt can be temporarily ignored by the counter is called 

Vector interrupt
Non maskable interrupt
Maskable interrupt
Low priority interrupt
      _____________________________________________________________________________________
A CPU generally handles an interrupt by executing an interrupt service routine

as soon as an interrupt is raised
by checking the interrupt register at the end of fetch cycle
by checking the interrupt register after finishing the executing the current instruction
by checking the interrupt register at fixed time intervals
      _____________________________________________________________________________________
A single instruction to clear lower 4 bits of the accumulator in 8085 assembly language is 

XRI OF H
A NI OH
X RI FOH
ANI OF H
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Which out of the following is not an alternative name for primary memory? 

Main memory
Primary memory
Internal storage
Mass storage
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Which of the following is a sequential access device

Hard disk
Optical disk
Tape
Flash memory
      _____________________________________________________________________________________
The ALU of a computer normally contains a number of high speed storage elements called 

Semi conductor
Register
Hard disk
Magnetic disk
      _____________________________________________________________________________________
The control unit of computer

Performs ALU operations on the data
Controls the operation of the output devices
Is a device for manually operating the computer
Direct the other unit of computers
      _____________________________________________________________________________________
WORM stands for

Write Once Read Memory
Wanted Once Read Memory
Wanted Original Read Memory
Write Original Read Memory
      _____________________________________________________________________________________
The hardware in which data may be stored for a computer system is called

Register
Memory
Chip
Peripheral
      _____________________________________________________________________________________
The Pentium processor was introduced

1991
1992
1993
1994
      _____________________________________________________________________________________
The circumferences of the two concentric disks are divided into 100 sections each. For the outer disk, 100 of the sections are painted red and 100 of the sections are painted blue. For the inner disk, the sections are painted red and blue in an arbitrary manner. It is possible to align the two disks so that of the sections on the inner disks have their colours matched with the corresponding section on outer disk.

100 or more
125 or more
150 or more
175 or more
      _____________________________________________________________________________________
Interrupts which are initiated by an I/O drive are 

Internal
External
Software
All of above
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Arithmetic shift left operation 

Produces the same result as obtained with logical shift left operation
Causes the sign bit to remain always unchanged
Needs additional hardware to preserve the sign bit
Is not applicable for signed 2s complement representation
      _____________________________________________________________________________________
Fetch_And_Add(X,i) is an atomic Read-Modify-Write instruction that reads the value of
memory location X, increments it by the value i, and returns the old value of X. It is used in the
pseudocode shown below to implement a busy-wait lock. L is an unsigned integer shared variable
initialized to 0. The value of 0 corresponds to lock being available, while any non-zero value corresponds to the lock being not available.
AcquireLock(L){
while (Fetch_And_Add(L,1))
L = 1;
}
ReleaseLock(L){
L = 0;
}
This implementation


fails as L can overflow
fails as L can take on a non-zero value when the lock is actually available
works correctly but may starve some processes
works correctly without starvation
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A control character is sent at the beginning as well as at the end of each block in the synchronous-transmission in order to 

Synchronize the clock of transmitter and receiver
Supply information needed to separate the incoming bits into individual character
Detect the error in transmission and received system.
Both (A) and (C).
      _____________________________________________________________________________________
The process of entering data into a storage location 

Causes variation in its address number
Adds to the contents of the location
Is called a readout operation
Is destructive of previous contents
      _____________________________________________________________________________________
Of the following, which best characterizes computers that use memory-mapped I/O?

The computer provides special instructions for manipulating I/O ports.
I/O ports are placed at addresses on the bus and are accessed just like other memory locations.
To perform an I/O operation, it is sufficient to place the data in an address register and call the channel to perform the operation.
Ports are referenced only by memory-mapped instructions of the computer and are located at hardwired memory locations.
      _____________________________________________________________________________________
The desirable characteristic of a memory system is 

Speed and reliability
Low power consumption
Durability and compactness
All of these
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In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from

( j mod v ) * k to ( j mod v ) * k + (k - 1)
( j mod v ) to ( j mod v ) + (k - 1)
( j mod k ) to ( j mod k ) + (v - 1)
( j mod k ) * v to ( j mod k ) * v + (v - 1)
      _____________________________________________________________________________________
Intel 80486 was introduced in

1985
1986
1987
1989
      _____________________________________________________________________________________
Which of the following are typical characteristics of a RISC machine?

Highly pipielined
Multiple register sets
Both a and b
None of these
      _____________________________________________________________________________________
The amount of ROM needed to implement a 4 bit multiplier is

64 bits
128 bits
1 Kbits
2 Kbits
      _____________________________________________________________________________________

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock
cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?


3.4
4.3
5.1
6.3
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A charge coupled device has

Low cost per bit
High cost per bit
Low density
None of these
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WHAT IS A REGISTER?

MEMORY
ARRAY
COUNTER
NONE
      _____________________________________________________________________________________
The bus which is used to transfer data from main memory to peripheral device is

Data bus
Input bus
DMA bus
Output bus
 
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